1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip evaluation, and more particularly, to IC chip evaluation using at-functional-speed testing with process coverage evaluation.
2. Background Art
At-functional-speed testing of integrated circuit (IC) chips is frequently used to verify the functionality and performance of product IC chips. During IC chip fabrication, process variations may alter how an IC chip functions and/or performs. Further, fabrication process parameters can vary drastically from one IC chip fabrication lot to another, and within a lot. In addition, operating conditions within an IC chip vary during operation. One challenge relative to at-functional-speed testing is that IC chips tested represent, or include, only a small sampling of the overall fabrication process and operation condition variations the IC chip might see. However, it is important for IC chip fabricators to understand performance of future IC chips regardless of the different variations. Each IC chip must function and perform at acceptable rates regardless of the variations. Therefore, the measurements attained during at-functional-speed testing must be accompanied by modeling of the IC chip with its variations, so that the effect of the variations on the specific IC chip can be accurately predicted. The results of the IC chips' at-functional-speed tests should guide the simulation and the simulation should guide the at-functional-speed testing. However, this functionality is not available in the prior art.
Testing the IC chips with varying operation conditions such as voltage and temperature can further improve the model accuracy (testing a chip while sweeping conditions like voltage and temperature is also called “shmooing”). Also, intentional fabrication process variations can further enhance the modeling accuracy (the intentional variations are created in stripes on the surface of the wafer, and this procedure is called “striping” of hardware). The varying voltage and temperature and intentional process variations validate the modeling methodology with the tested IC chip.
One approach to this problem is to apply at-functional-speed tests to the IC chip and then to compare the timing obtained with a static timing model using only a single worst case process point. Conventionally, the at-functional-speed tests applied are either functional tests, transition-fault tests or path tests based on static timing analysis prediction of the worst case paths. Other approaches include at-functional-speed robust path tests generated using a statistical timing model based on injection of random transition faults into the circuit of the IC chip. Some approaches also use the results of at-functional-speed test for diagnosis of random defects based on statistical timing. However, none of the current approaches identifies the amount of variation covered by a set of at-functional-speed test patterns, nor do they determine the quality of the at-functional-speed tests from a process coverage standpoint. In addition, current approaches do not correlate manufacturing testing results with timing model accuracy based on changes in voltage, frequency or temperature, or based on process variations.